Publications and Patents

Recent Publications:

  1. C. K. Matcha, S. S. Garani, “2D Linear Detector Based on Generalized Belief Propagation Algorithm”, in Annual Allerton Conference on Communication, Control, and Computing (Allerton), Oct. 2018 (accepted).
  2. A. B. Nair, A. Mondal and S. S. Garani, “A Low-complexity Hardware AWGN Channel Emulator on FPGA using Central Limit Theorem” in IEEE Int. Midwest Symp. on Circuits and Syst, Windsor, Canada, Aug. 2018.
  3. P. Gowgi, A. Machireddy and S. S. Garani, “Priority-based Soft Vector Quantization Feature Maps”, in IEEE Int. Joint Conf. on Neural Networks (IJCNN), Rio, Brazil, July 2018.
  4. A. Machireddy and S. S. Garani, “Data Dependent Adaptive Prediction and Classification of Video Sequences”, in Int. Conf. on Artificial Intelligence and Soft Computing (ICAISC), Zakopane, Poland, June 2018.
  5. P. J. Nadkarni, A. Raina and S. S. Garani, “Recovery of distributed quantum information from a node failure using graph states,” in Quantum Communication and Information Technology Workshop, IEEE GLOBECOM, Singapore, December 2017.
  6. P. J. Nadkarni and S. S. Garani, “Entanglement Assisted Binary Quantum Tensor Product Codes”, in IEEE Information Theory Workshop, Kaohsiung, Taiwan, Nov. 2017.
  7. A. Raina, P. J. Nadkarni and S. S. Garani, “Recovery of Distributed Quantum Information in Quantum Networks”, in Frontiers in Optics, Washington D.C., Sep. 2017.

 

Journal Special Issue (Editorial):

  1. IEEE J-SAC 2016 – Channel Modeling, Coding and Signal Processing for Novel Physical Memory Devices and Systems (http://www.comsoc.org/jsac).

 

Selected Publications:

  1. P. Gowgi and S. S. Garani, “Temporal Self-Organization: A Reaction-Diffusion Framework for Spatiotemporal Memories,” in IEEE Trans. on Neural Netw. and Learning Syst., Jul. 2018 (early access).
  2. S. S. Garani, L. Dolecek, J. Barry, F. Sala and B. Vasic, “Signal Processing and Coding Techniques for 2-D Magnetic Recording: An Overview”, in Proc. of the IEEE., vol. 106, no. 2, pp. 286-318, Feb. 2018. 
  3. A. Mondal, S. Thatimattala, V. K. Yalamaddi and S. S. Garani, “Efficient Coding Architectures for Reed-Solomon and Low-Density Parity-Check Decoders for Magnetic and Other Data Storage Systems,” in IEEE. Trans. Magn., vol. 54, no. 2, pp. 1-15, Feb. 2018.
  4. C. K. Matcha, S. Roy, M. Bahrami, B. Vasic and S. S. Garani, “2D LDPC Codes and Joint Detection and Decoding for Two-Dimensional Magnetic Recording,” in IEEE Trans. on Magn., vol. 54, no. 2, Feb. 2018.
  5. C. K. Matcha and S. S. Garani, “Joint Timing Recovery and Signal Detection for Two-Dimensional Magnetic Recording,” in IEEE. Trans. Magn., vol. 53, no. 2, Feb. 2017.
  6. C. K. Matcha and S. S. Garani, “Defect Detection and Burst Erasure Correction for TDMR,” in IEEE. Trans. Magn., vol. 52, no. 11, Nov. 2016.
  7. S. Datta and S. S. Garani, “Design Architecture of a Two-Dimensional Separable Iterative Soft Output Viterbi Detector,” in IEEE. Trans. Magn., Jan. 2016.

 

Patents:

  1. Method and apparatus for joint adaptation of two-/multi- dimensional equalizer and partial response target, United States Patent No. 10,026,441, Shayan Srinivasa Garani, Chaitanya Kumar Matcha, Arnab Dey, Jul. 2018.
  2. Identifying a defect in a data-storage medium, United States Patent No. 9,324,370, Shayan G. Srinivasa and Sivagnanam Parthasarathy, 2016.
  3. Method and system for monitoring data channel to enable use of dynamically adjustable LDPC coding parameters in a data storage system, Patent No. 9,214,963, Shayan Garani Srinivasa, Kent D. Anderson, Anantha Raman Krishnan, Guangming Lu, Shafa Dahandeh, Andrew J. Tomlin, Dec. 2015.
  4. Systems and methods for improved encoding of data in data storage devices, Patent No. 9,203,434, Shayan G. Srinivasa, Dec. 2015.
  5. Decoding data stored in solid-state memory, Patent No. 8,990,668, with Anantha Raman Krishnan and Kent Anderson, Mar. 2015.
  6. Data storage device tracking log-likelihood ratio for a decoder based on past performance, Patent No. 8,856,615, with Anantha Raman Krishnan, Kent Anderson and Shafa Dahandeh, Oct. 2014.
  7. Methods and devices for joint two-dimensional self-iterating equalization and detection, Patent No. 8,760,782, with Yiming Chen, June 2014.
  8. Constrained on-the-fly interleaver address generation, Patent No. 8,625,220, with Sivagnanam Parthasarathy and Sudha Thipparthi, Jan. 2014.
  9. Methods and devices for two-dimensional iterative multi-track based MAP detection, Patent No. 8,582,223, with Yiming Chen, Nov. 2013.
  10. Encoding apparatus, system and method using LDPC codes, Patent No. 8,397,125, Shayan G. Srinivasa, Mar. 2013.
  11. Adaptive data dependent noise prediction, Patent No. 8,290,102, with Mustafa Kaynak, Stefano Valle and Sivagnanam Parthasarathy, 2012.
  12. Interlaced iterative system design for 1K-byte block with 512 byte LDPC code words, Patent No. 8,255,768, with Xinde Hu, Sivagnanam Parthasarathy, Anthony Weathers and Richard Barndt, 2012.
  13. Channel constrained code aware interleavers, Patent No. 8,055,973, with Nicholas Richardson and Xinde Hu, 2011.